Cell-based integrated circuits make use of a library of basic building blocks which are called cells or standard cells. Using cells from the library, larger, more complex functions can be realized. In contrast to transistor-level in situ customization of cell designs, the cells are treated as black box entities by the design and verification tools and are fully characterized for timing, noise, reliability, etc.
In cell-based integrated circuits, for example, baseband chips, spare cells can be provided in a chip to fix post tape out bugs. Such spare cells need to have their inputs to be defaulted to a constant voltage. Because of the generic design methodology at the so-called RTL (Register Transfer Level) level, it is currently quite common to end up with many unconnected inputs which by default will be tied to “0” or “1”. It may happen that a particular macro architecture needs “constant voltage” at some inputs for its optimal synthesis.
In integrated circuits, particularly in cell-based integrated circuits, it may also happen that not all inputs of a logic gate are need to be used or connected to the preceding stages. In such cases, the respective inputs are either grounded or connected to supply so that they do not interfere with the intended operation of the logic gate. Until now, it was possible to connect such unused or default inputs directly to the supply or ground rail. However, with advancing technology, the shrinking gate oxide thickness prevents such direct connections of the logic gate to the voltage supply (VDD) rail or ground (VSS) rail due to electrostatic discharge (ESD) considerations.
In integrated circuits, in particular in cell-based circuits, it may also happen that entire blocks of logic are switched off when not needed in order to save power in critical circuits and to extend battery life. This is achieved by disconnecting the VDD (supply) rail or VSS (ground) rail from the logic block under consideration. However, when the logic block is again connected to the power rails, the logic block must be restored to its default state as quickly as possible. This process demands a lot of current in a short time as all capacitances associated with the block need to be recharged. These current spikes, together with the inductances and resistances of the overall power network will cause excessive voltage drops, entailing both over overshooting and undershooting, and affect the neighboring logic blocks that have not been switched off.